Lithographic apparatuses can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask).
As semiconductor manufacturing processes continue to advance, the dimensions of circuit elements have continually been reduced while the amount of functional elements, such as transistors, per device has been steadily increasing over decades, following a trend commonly referred to as ‘Moore's law’. At the current state of technology, critical layers of leading-edge devices are manufactured using optical lithographic projection systems known as scanners that project a mask image onto a substrate using illumination from a deep-ultraviolet laser light source, creating individual circuit features having dimensions well below 100 nm, i.e. less than half the wavelength of the projection light.
This process in which features with dimensions smaller than the classical resolution limit of an optical projection system are printed, is commonly known as low-k1 lithography, according to the resolution formula CD=k1×λ/NA, where λ, is the wavelength of radiation employed (currently in most cases 248 nm or 193 nm), NA is the numerical aperture of the projection optics, CD is the ‘critical dimension’—generally the smallest feature size printed—and k1 is an empirical resolution factor. In general, the smaller k1, the more difficult it becomes to reproduce a pattern on the wafer that resembles the shape and dimensions planned by a circuit designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps are applied to the projection system as well as to the mask design. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting masks, optical proximity correction (OPC) in the mask layout, or other methods generally defined as ‘resolution enhancement techniques’ (RET).
Double patterning lithography (DPL) is one of the methods to effectively overcome the resolution limit of lithographic exposure apparatus, especially, when further increase of NA is no longer a feasible option. In general, in double patterning lithography, dense target patterns, whose individual feature CD and/or inter-feature pitch is below the resolution limit of the lithography apparatus, are split in two parts (this process is referred to as “coloring”), such that, independently in each part, there is no resolution-related problems to overcome during pattern printing. The parts are patterned sequentially, interspersing features printed in the first lithography with features printed in the second lithography, to reproduce the entire pattern. Double patterning lithography may adopt a positive tone or a negative tone, as discussed, for example, in the reference, titled, “Positive and negative tone double patterning lithography for 50 nm flash memory,” by Lim et al., published in Proceedings of SPIE vol. 6154, (2006). However, alignment of various parts of the target pattern with respect to each other is a challenging process in existing double patterning lithography processes, and is often associated with low yield due to alignment error.
To reduce the alignment error, a spacer has been used in the double patterning lithographic process flow. In one example, an amorphous carbon spacer is added, as described in an article titled, “Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool,” by Jung et al., published in Proceedings of SPIE vol. 6156 (2006). Spacer-assisted double patterning lithography method has been used for realizing volume manufacturing of the 32 nm technology node. Still, overlay control issue remains a source of error in existing spacer-assisted double patterning methods, especially for critical device features, such as, a polysilicon gate. Conventional spacer-assisted positive tone method can only print patterns with a single CD that are self-aligned. Additional mask and overlay-critical steps are needed for multiple CDs. Conventional spacer-assisted negative tone method can print different CDs, but self-alignment accuracy is often unacceptable without additional fine-tuning of a subsequent trimming method.
What is needed is a simpler alignment method, such as, a comprehensive automatic self-alignment method, to pattern multiple parts of a target pattern. Additionally, the self-alignment method should overcome or simplify overlay-related problems by adopting a suitable process flow that does not necessarily need to differentiate between critical and non-critical features of the target pattern, and therefore, avoids the need for stitching different parts of the target pattern.